The present invention is generally related to the fabrication of integrated circuits (ICs) and, more specifically, to the fabrication of a lead germanate ferroelectric structure having an electrode of layered noble metals.
Platinum (Pt) and other noble metals are used in IC ferroelectric capacitors. The use of noble metals is motivated by their inherent chemical resistance. This property is especially desirable under high temperature oxygen annealing conditions, such as those seen in the fabrication of ferroelectric capacitors. In addition, chemical interaction between noble metals and ferroelectric materials such as perovskite metal oxides, is negligible.
The above-mentioned noble metals are used as conductive electrode pairs separated by a ferroelectric material. One, or both of the electrodes are often connected to transistor electrodes, or to electrically conductive traces in the IC. As is well known, these ferroelectric devices can be polarized in accordance with the voltage applied to the electrode, with the relationship between charge and voltage expressed in a hysteresis loop. When used in memory devices, the polarized ferroelectric device can be used to represent a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d. These memory devices are often called ferro-RAM, or FeRAM. Ferroelectric devices are nonvolatile. That is, the device remains polarized even after power is removed from the IC in which the ferroelectric is imbedded.
There are problems in the use of metal, even noble metal electrodes. Pt, perhaps the widely used noble metal, permits the diffusion of oxygen, especially during high temperature annealing processes. The diffusion of oxygen through Pt results in the oxidation of the neighboring barrier and substrate material. Typically, the neighboring substrate material is silicon or silicon dioxide. Oxidation can result in poor adhesion between the Pt and neighboring layer. Oxidation can also interfere with the conductivity between neighboring substrate layers. Silicon substrates are especially susceptible to problems occurring as a result of oxygen diffusion. The end result may be a ferroelectric device with degraded memory properties. Alternately, the temperature of the IC annealing process must be limited to prevent the degradation of the ferroelectric device.
Various strategies have been attempted to improve the interdiffusion, adhesion, and conductivity problems associated with the use of noble metals as a conductive film in IC fabrication. Titanium (Ti), titanium oxide (TiO2), and titanium nitride (TiN) layers have been interposed between a noble metal and silicon (Si) substrates to suppress the interdiffusion of oxygen. However, Ti layers are generally only effective below annealing temperatures of 600 degrees C. After a 600 degree C annealing, Pt diffuses through the Ti layer to react with silicon, forming a silicide product. Further, the Pt cannot stop the oxygen diffusion. After a high temperature annealing, a thin layer of silicon oxide may be formed on the silicon surface, which insulates contact between silicon and the electrode.
Other problems associated with the annealing of a Pt metal film are peeling and hillock formation. Both these problems are related to the differences in thermal expansion and stress of Pt with neighboring IC layers during high temperature annealing. A layer of Ti overlying the Pt film is known to reduce stress of the Pt film, suppressing hillock formation.
Ir has also been used in attempts to solve the oxygen interdiffusion problem. Ir is chemically stable, having a high melting temperature. Compared to Pt, Ir is more resistant to oxygen diffusion. Further, even when oxidized, iridium oxide remains conductive. When layered next to Ti, the Ir/Ti barrier is very impervious to oxygen interdiffusion. However, Ir can diffuse through Ti. Like Pt, Ir is very reactive with silicon or silicon dioxide. Therefore, a bilayered Ir/Ti or Ir/TiN barrier is not an ideal barrier metal.
Pb5Ge3O11 is a promising ferroelectric material candidate for nonvolatile memory, such as one-transistor (1T) applications, because of its moderate polarization and relative low dielectric constant. But, this material is a low symmetry ferroelectric material, and it is widely believed that spontaneous polarization exists only along the c-axis. Furthermore, in the PbOxe2x80x94GeO2 system, the stability range for the Pb5Ge3O11 phase is very limited. Even a relatively small deviation in composition, or in growth temperature, can lead to the formation of other lead germanate (PGO) compounds, or phases. Therefore, successful use of this ferroelectric material is dependent upon deposition processes and the adjoining electrode material.
A suitable bottom electrode is required for depositing useful lead germanate (Pb5Ge3O11) ferroelectric thin films. The bottom electrode must have good adhesion with the substrate, good electrical conductivity, and good barrier properties with respect to oxygen and lead. A good bottom electrode must also improve the fatigue degradation, and reduce the leakage current, of the lead-based ferroelectric thin film. From the processing point of view, the bottom electrode should provide a preferred nucleation and growth surface for the c-axis oriented lead germanate (Pb5Ge3O11) thin film at a relative low MOCVD temperature.
Single-layer platinum is widely used as the bottom electrode in PZT and SBT based nonvolatile ferroelectric memories. However, oxygen and elements such as lead can easily diffuse through Pt and react with barrier layers (Ti, TiN) and/or the substrate (Si or Si02), all of which are susceptible to oxidation. Deleterious oxidation leads to bad adhesion with the substrate, a poor interface between platinum and ferroelectric layers, and a poor interface between platinum and the substrate layers.
Further, severe fatigue is an inherent problem associated with ferroelectric thin films, which is not improved by using a single-layer platinum electrode. Fatigue degradation is thought to be due to the domain pinning by space charge, caused by oxygen vacancy entrapment at the interface between the ferroelectric film and the electrode. It is believed that fatigue properties can be significantly improved by using a conducting oxide electrode to prevent space charge formation at the interface. Finally, hillocks are typically found on the surface of single-layer platinum electrodes during depositing of ferroelectric thin film. The hillocks are caused by stress internal to the platinum film. Hillocks result in increased leakage currents, or even device shorts.
Single-layer iridium bottom electrodes are also used in PZT and SBT based devices. Iridium bottom electrodes have superior barrier properties with respect to lead and oxygen, as well as good adhesion with the substrate. However, higher process temperatures are required for MOCVD c-axis oriented lead germinate (Pb5Ge3O11) thin films deposition processes, comparing to the platinum electrode. The MOCVD temperature range to deposit c-axis oriented lead germanate (Pb5Ge3O11) thin film on the Ir electrode is 500-600xc2x0 C. Further, a lower nucleation site density causes a very rough lead germanate (Pb5Ge3O11) thin film surface, as compared to the film deposited on platinum electrode. Finally, hillock formation on the surface of the iridium electrode is still observed during MOCVD processing.
Metal oxide electrodes such as RuO2 are used for PZT based nonvolatile memory to improve the fatigue degradation. But RuO2 electrodes cause an increase in the leakage current. An oxide/platinum double-layer electrode reduces the leakage current, and improves the barrier properties and hillock problem. However, the leakage current is still larger than that of using a single-layer platinum electrode. Further, a thicker oxide layer is formed, resulting in a higher sheet resistance.
Several other oxygen barrier layers exist including a conductive exotic-nitride layer underneath a platinum layer (Tixe2x80x94Alxe2x80x94N), a noble-metal-insulator-alloy barrier layer (pd-Sixe2x80x94N), and similar variations. These oxide barriers require more complicated process steps and a multilayer electrode in order to meet the requirement for a bottom electrode. A Pt/IrO2 electrode is used in SBT based devices. However, the Pt/IrO2 electrode is not very suitable for lead-based thin films. This is because a thin oxide layer is still needed between the ferroelectric film and the platinum electrode in order to improve the fatigue degradation.
Co-pending application Ser. No. 09/263,595, entitled xe2x80x9cIridium Conductive Electrode/Barrier Structure and Method for Samexe2x80x9d, invented by Zhang et al., and filed on Mar. 5, 1999, discloses a multilayered Ir/Ta film that is resistant to interdiffusion.
Co-pending application Ser. No. 09/263,970, entitled xe2x80x9cIridium Composite Barrier Structure and Method for Samexe2x80x9d, invented by Zhang et al., and filed on Mar. 5, 1999, discloses a composite Ir film that is resistant to interdiffusion, and stable during high temperature annealing.
Co-pending application Ser. No. 09/316,646, entitled xe2x80x9cComposite Iridium Barrier Structure with Oxidized Refractory Metal Companion Barrier and Method for Samexe2x80x9d, invented by Zhang et al., and filed on May 21, 1999, discloses a Ir composite film with an oxidized transitional metal barrier layer that maintains conductivity and structural stability after high temperature annealing in an oxygen environment.
Co-pending application Ser. No. 09/316,661, entitled xe2x80x9cComposite Iridium-Metal-Oxygen Barrier Structure with Refractory Metal Companion Barrier and Method for Samexe2x80x9d, invented by Zhang et al., and filed on May 21, 1999, discloses a Ir composite film that maintains conductivity and structural stability after high temperature annealing in an oxygen environment.
In co-pending patent application Ser. No. 09/301,435, entitled xe2x80x9cMulti-Phase Lead Germanate Film and Deposition Methodxe2x80x9d, invented by Tingkai Li et al., filed on Apr. 28, 1999, a second phase of Pb3GeO5 is added to the Pb5Ge3O11, increasing polycrystalline grain sizes, without c-axis orientation. The resultant film had increased Pr values and dielectric constants, and decreased Ec values. Such a film is useful in making microelectromechanical systems (MEMS), high speed multichip modules (MCMs), DRAMs, and FeRAMs,
In co-pending patent application Serial No. 09/301,420, entitled xe2x80x9cC-Axis Oriented Lead Germanate Film and Deposition Methodxe2x80x9d, invented by Tingkai Li et al., filed on Apr. 28, 1999, a PGO film is disclosed. This film has primarily a c-axis orientation with a smaller Pr value, smaller dielectric constant, and larger Ec value. Such a film is useful in making 1T memories.
In co-pending patent application Ser. No. 09,302,272, entitled xe2x80x9cEpitaxially Grown Lead Germanate Film and Deposition Methodxe2x80x9d, invented by Tingkai Li et al., filed on Apr. 28, 1999, an epitaxial grown PGO film is disclosed with extremely high c-axis orientation. As a result, high Pr and Ec values, as well as lower dielectric constant, is obtained. Such a film is useful in 1T, and one transistor/one capacitor (1T/1C) FeRAM applications.
In co-pending patent application Ser. No. 09,301,434, entitled xe2x80x9cFerroelastic Lead Germanate Thin Film and Deposition Methodxe2x80x9d, invented by Tingkai Li et al., filed on Apr. 28, 1999, a CVD Pb3GeO5 film is described having improved ferroelastic properties useful in making MEMS and MCMs. The above-mentioned co-pending patent applications are incorporated herein by reference.
It would be advantageous if a ferroelectric electrode could be fabricated that incorporated the best features of Ir and Pt.
It would be advantageous if alternate methods were developed for the use of Ir and/or Pt as conductors, conductive barriers, or electrodes in IC fabrication. It would be advantageous if the Ir and Pt could be used without interaction to an underlying Si substrate.
It would be advantageous if an Ir or Pt film could be altered to improve interdiffusion properties. Further, it would be advantageous if this improved type of Ir or Pt film could be layered with an interposing film to prevent the interaction of Ir or Pt with a silicon substrate. It would be advantageous if an interposing film could prevent interdiffusion between the electrode and the ferroelectric material.
Accordingly, a ferroelectric device is provided comprising a silicon substrate, a first electrode layer of Ir overlying the substrate, and a second electrode layer of Pt overlying the first electrode layer. The first and second electrode layers have a combined thickness of about 100 to 400 nm, and are used to improve adhesion, barrier properties, and the uniformity of the PGO film.
A first barrier layer of lrO2 overlies the second electrode layer, to improve the interface to PGO film, and limit the diffusion of oxygen into the first and seconds electrode layers. A lead germanate (PGO) film having a Pb5Ge3O11 phase of about 10 to 100% overlies the first barrier layer. Optionally, the PGO film is epitaxially grown Pb5Ge3O11 phase. In this manner, a ferroelectric device is formed having low leakage current and a resistance to fatigue.
A second barrier layer of a material such as Ti, Ta, TiN, TaN, or a ternary nitride including nitrogen and a refractory metal, such as TiSiN or TaSiN, having a thickness of about 10 to 100 nanometers (nm), is interposed between the substrate and the first electrode layer to minimize interdiffusion between the substrate and the electrode layers. Further, adhesion between the substrate and the electrode layers is improved by using the second barrier.
Ultimately, the ferroelectric device forms a capacitor with the addition of a conductive film top electrode overlying the PGO film. The top electrode optionally comprises a third Pt electrode layer overlying the PGO film, and a fourth Ir electrode layer overlying the third electrode layer to form a second layered electrode. When a layered top electrode is used, a third barrier layer is interposed between the PGO film and the third electrode layer to improve the interface with the underlying PGO film.
Also provided is a method of forming a ferroelectric device on a substrate comprising the steps of:
a) forming the Ir electrode layer overlying the substrate to a thickness of approximately 150 nm.;
b) forming the Pt electrode layer overlying the first electrode layer to a thickness of approximately 50 nm.;
c1) forming a first IrO2 barrier layer overlying the second electrode layer to a thickness of approximately 15 nm; and
c2) forming a second barrier layer of selected from the group consisting of consisting of Ti, Ta, TiN, TaN, and ternary nitrides including nitrogen and a refractory metal, interposed between the substrate and the first electrode layer, having a thickness of approximately 25 nm;
d) forming a PGO layer overlying the first barrier layer film, to a thickness in the range of approximately 100-200 nm, through MOCVD processes at a temperature in the range of approximately 400 to 550 degrees C.
There are three different processes for forming the first barrier layer. In one process, Step c1) includes annealing the first and second electrode layers to form a first barrier layer oxide overlying the second electrode layer. In a second process, Step c1) includes using processes selected from the group consisting of PVD, CVD, and MOCVD to deposit a first barrier layer of IrO2. In a third process, Step c1) includes forming lrO2 in preparation for an MOCVD process in Step d), by preflowing oxygen at a flow rate in the range of approximately 2000 to 4000 sccm, at a growth chamber pressure of approximately 10 torr, a substrate temperature in the range of approximately 400 to 550 degrees C, for a duration of approximately 10 to 15 minutes, whereby the first barrier layer is formed in situ.
Steps a) and b) includes depositing the first and second electrode layers through processes selected from the group consisting of e-beam evaporation, CVD, PVD, and MOCVD, at a temperature in the range of approximately 200-300 degrees C.
When a capacitor is formed, further steps following Step d), of:
d1) forming a third barrier layer of IrO2 overlying the PGO film formed in Step d), whereby the interface between the PGO film and the third and fourth electrode layers is improved;
e) forming a third electrode layer overlying the PGO film; and
f) forming a fourth electrode layer overlying the third electrode layer, whereby a ferroelectric capacitor is formed.